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 L&T Recruiting M.tech fresher (VLSI) for Post Graduate Engineer Trainee position.
Location: Bangalore,Chennai fresherscafe.com
Job Profile:
ASIC Design : Verilog/VHDL, RTL coding, ASIC/FPGA Synthesis, Place and route, Timing closure fresherscafe.com
ASIC Verification : Verilog/System Verilog/Vera/C, ASIC Functional verification, Test bench Development, Timing Simulations fresherscafe.com
Backend : ASIC synthesis, Place and Route, Floor plan, Timing closure, Equivalence checking, Power Plan and Analysis.
How to apply: To apply click HERE |
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